1. Field of the Invention
The present invention relates to a semiconductor apparatus and particularly to a semiconductor apparatus including an internal circuit and a pad.
2. Description of Related Art
With rapid advancement of smaller and more sophisticated electronic equipment, more highly integrated semiconductor apparatus is under development. Further, higher manufacturing yield and higher quality are demanded for high integration and high density semiconductor apparatus.
FIG. 10 shows the cross-section of a bonding pad and its vicinity in a conventional multi-layer semiconductor chip. The bonding pad 101 is located in the peripheral part of the semiconductor chip. For example, the bonding pad 101 may be placed in a fill cell placed in the semiconductor chip.
This specification normally uses the term “fill cell” to refer to a cell which does not include a diffusion device such as a transistor and not perform a logical operation. The fill cell may be placed for layout purposes, such as in order to fill the gap of a buffer cell or the like or to connect a ground line or a power supply line to a buffer cell or other cells. In some cases, the fill cell may include a diffusion device as needed.
As shown in FIG. 10, a metal layer 131 lies in the surface of the semiconductor chip. A cover layer 106 covers the metal layer 131. The cover layer 106 has an opening where the metal layer 131 is exposed. The metal layer 131 which is exposed in this opening serves as the bonding pad 101.
Below the metal layer 131, metal layers 132, 133, 134, and 135 are stacked with an interlayer insulating film, not shown, interposed therebetween. The metal layers 132 to 135 serve as line layers constituting an internal circuit or the like of the semiconductor chip.
The bonding pad 101 is connected to a lead frame by wire bonding, for example, so as to electrically connect the internal circuit and an external electrode. Since the wire bonding is formed in the central part of the bonding pad 101, an impact of the bonding reaches below the bonding pad 101. For example, the wire bonding process brings a bonding ball into contact with the bonding pad 101 and applies pressure and supersonic vibration thereon, thereby bonding them together. This process makes an impact on the bonding pad 101.
This impact gives damage to a line and an interlayer insulating film located below the bonding pad 101, causing lower yield. Specifically, it causes problems such as crack of the interlayer insulating film, short-circuit of a pad and a lower layer line, and short-circuit of lower layer lines. Further, if a diffusion device exists below the bonding pad 101, the bonding impact can cause the operating characteristics of the diffusion device to deteriorate.
Furthermore, a wafer inspection process performs probing by bringing a probe into contact with the central part of the bonding pad 101. If the stylus force of the probe is high so as to ensure electrical continuity, the bonding pad 101 receives an impact, which causes the same problems as the bonding. On the other hand, reduction of the number of contacts or the stylus force to suppress the damage in probing results in lower test efficiency and reliability.
To overcome the above problems, Japanese Unexamined Patent Application Publication No. 2002-16069, for example, proposes a structure where a plurality of via holes are arranged in a two-dimensional array between doubled pads. This structure, however, cannot sufficiently reduce the effect of bonding and probing. For example, if the metal layers 131 and 132 are doubled pads, the impact of bonding or the like on the metal layer 133 placed below can be reduced to a certain degree; however, the above problems can still occur when the metal layer is made of a soft material such as Al or the bonding or probing force is large.
On the other hand, as a chip size becomes smaller, a pitch between pads decreases and a pad size is also becomes smaller. To meet a demand for smaller pitches, Japanese Unexamined Patent Application Publication No. 2003-163267, for example, proposes a semiconductor apparatus having pads arranged in a staggered pattern in the peripheral part of a semiconductor chip.
FIGS. 11A and 11B are top views illustrating the bonding pads arranged in a staggered pattern and their vicinity. In FIGS. 11A and 11B, bonding pads 101a, 101b, and 101c are located in the outer side of the semiconductor chip. They are electrically connected to an internal circuit by lead-in lines 111a, 111b, and 111c, respectively. Further, bonding pads 112a, 112b, and 112c are located in the inner side of the semiconductor chip and electrically connected to the internal circuit by lead-in lines 113a, 113b, and 113c, respectively.
A bonding wire or the like is connected to a bonding position 114 in the central part of the bonding pad 101b, thereby electrically connecting an external electrode and the internal circuit of the semiconductor chip.
FIG. 11A illustrates the case of forming the bonding pads 101a to 10c, the lead-in lines 111a to 111c, the bonding pads 112a to 112c, and the lead-in lines 113a to 113c in the same layer. In this case, it is necessary to form the lead-in lines 111a to 111c so as not to touch the bonding pads 112a to 112c. Thus, the width of the lead-in lines 111a to 111c is limited by the position, shape and so on of the bonding pads 112a to 112c. Therefore, as the pitch of the bonding pads 112a to 112c decreases, the width of the lead-in lines 111a to 111c decreases accordingly. If supplying power from the bonding pad 101, since the power supply capacity is proportional to the width of the lead-in line, the decrease in the width of the lead-in line leads to a decrease in the power supply capacity. If the lead-in line is used to supply an input/output signal instead of power, signal degradation occurs.
FIG. 11B illustrates the case of forming the lead-in lines 111a to 111c in a layer lower than the bonding pads 112a to 112c. Since the lead-in lines 111a to 111c and the bonding pads 112a to 112c are formed in different layers, it is possible to increase the width of the lead-in lines 111a to 111c without the limitation of the bonding pads 112a to 112c. However, since the lead-in lines 111a to 111c are not formed in the top layer and the lower layer is thinner than the top layer, the power supply capacity can decrease even if the lead-in lines 111a to 111c are wide.
As described above, the present invention has recognized that conventional semiconductor apparatus have the problems that yield decreases due to an impact of bonding and probing if an internal circuit exists below a pad, and that power supply voltage drops or input/output signal deteriorates due to pad arrangement.